Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

I see. The multi dimensional bit vectors are fine, and can be easily described with generics/parameters, although you have to be careful. I use the std_logic_2D type as defined in the 'lpm' library a lot. The record type indeed may present a problem. But a record could be 'flattened' to a std_logic_vector on output and 'rebuilt' on entry? Although this may be less straightforward, I recall having tried something with records and stumbled ...