Honored ContributorHello friends,
I need to feed LPM_ADD_SUB module which is on 37 bits with only 21 bits and the rest tied to gnd (MSB's). The problem is I can't figure out how, since those 21 bits are from LPM_MULT and the bus name is result[21..0] and the input of LPM_ADD_SUB wants datab[36..0]. I know this is simple but I haven't found yet and keep me nervous :) Thanks,
Honored Contributorok, still isn't working, I wrote a small verilog to concatenate buses like that
module conv21to37(in,out);
input in;
output out;
assign out = {16'b0000000000000000,in};
endmodulemodule conv21to37(in,out);
input in;
output out;
assign out = {16'b0000000000000000,in};
endmodulepletz, thank you very much, it was my mistake.
the bus explode / combine worked like expected from schematic, but the error was generated by 2'nd LPM_MULT instance, on which I was used copy - paste instead of re-generate a new one with wizard. thanks again for example,
