schematic, bus explode, please

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ok, still isn't working, I wrote a small verilog to concatenate buses like that

module conv21to37(in,out);
input in;
output out;
assign out = {16'b0000000000000000,in};
endmodule

But Quartus keep telling me

Error: Port "datab[0]" does not exist in macrofunction "inst13"

Error: Port "datab[10]" does not exist in macrofunction "inst13"

Error: Port "datab[11]" does not exist in macrofunction "inst13"

Error: Port "datab[12]" does not exist in macrofunction "inst13"

Error: Port "datab[1]" does not exist in macrofunction "inst13"

Error: Port "datab[2]" does not exist in macrofunction "inst13"

Error: Port "datab[3]" does not exist in macrofunction "inst13"

Error: Port "datab[4]" does not exist in macrofunction "inst13"

Error: Port "datab[5]" does not exist in macrofunction "inst13"

Error: Port "datab[6]" does not exist in macrofunction "inst13"

Error: Port "datab[7]" does not exist in macrofunction "inst13"

Error: Port "datab[8]" does not exist in macrofunction "inst13"

Error: Port "datab[9]" does not exist in macrofunction "inst13"

The macrofunction "inst13" is a LPM_MULT which is output 21 bits that I want to send into LPM_ADD_SUB which has a 37 bit bus on datab[36..0]

Any idea?

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Hi,

have a look to the small project.

Kind regards

GPK