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Altera_Forum
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11 years ago

SCFIFO wrreq and rdreq synchronisation

Hi folks, just a quick question (hopefully), In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks Tricky.

You make a fair point, and it is probably worth my while bringing the async clock source into the FPGA.

Many thanks once again.

deBoogle