Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

SCFIFO wrreq and rdreq synchronisation

Hi folks, just a quick question (hopefully), In the SCFIFO megafunction I want to know if the wrreq and rdreq signals are synchronised to the clock input. That is to say, if I clock the FIFO...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Your idea could work, as long as you only use either the rising or falling edge pulses as the read/write request.

But Personally I would want the system clock to be > 2x async clock for this. Anything less and you're going to loose the bandwidth.

And anyhow, why take the risk of a difficult to constrain clock domain crossing with all the possible bugs, when you could use an IP designed for this very purpose (the DCFIFO).