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Altera_Forum
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9 years ago

Same VHDL block RAM inferring file, different results

Hi, I have the following VHDL file to infer a true dual port, single clock block RAM. I believe that it is according to Altera's guidelines. I have Quartus 16.02 Build 222 07/20/2016. When ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I don't know if this is what you want to do, but to get the most optimal results in hardware without having to futz with code, you could implement the RAM using the block RAM IP core.