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Altera_Forum
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9 years ago

Same VHDL block RAM inferring file, different results

Hi, I have the following VHDL file to infer a true dual port, single clock block RAM. I believe that it is according to Altera's guidelines. I have Quartus 16.02 Build 222 07/20/2016. When ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

It is probably the fact you have the write enable blocking the read side the of ram from occuring. Stop making doutN depend on the write enable.

Also, rams do not have a global enable, so remove this. use the enable externally to the ram.

edit: actually, its the passthrough you have designed. There is no passthrough on the rams. If you want a write-before read behaviour then use a shared variable for the ram, rather than signal.