Same project, different behaviour

Hi all, I have a StratixII Development Kit (EPS60 not ROHS). I have made two different project with same modules and parameters (same clock, same core, etc...). The first project was made from scratch by me. The second project is a modified version of a full_featured project made by Altera. The problems were different :

1) When I compiled my project (from scratch) with clock 55 MHz, the Quartus has given to me an error of timing requirements, but with modified full_featured I can increase the PLL clock out until 80 MHz.

2) Then I've compiled the uClinux kernel for the projects. With the modified full_featured the hardware is detected properly, but the uClinux kernel for the my project doesn't detecte the lan and the compactFlash (lan91c111 and CompactFlash SanDisk)

Did I forget some options about compiling ? Can someone help me ?

P.S. The only difference,that I noticed, betwen the projects is :

1) Address map

2) Top Level-entity (I use a Block Diagram, where I import the NiosII Core)

Sorry for my horrible english and thanks in advice.