safe state machines

Hello,

In the past, Altera recommended (in an older version of the Quartus handbook) to always explicitly specify the default state of state machines, to ensure that whenever a state machine jumps into some illegal state (as a result of a timing glitch or a SEU), it will at least return to a valid state quickly.

In VHDL, it translates to (assume the machine has only two valid states):

case (my_state) is
  when state_1 =>
    -- do stuff
  when state_2 =>
    -- do other stuff 
  when others =>
    my_staet <= state_1;
end case;

The key here is the transition in "others", which isn't strictly required because the case covers all the real cases. However, this is important in "safe state machine" design.

But now I've seen other recommendations in the Quartus handbook. The latest edition says that Quartus will ignore such explicit transitions. Instead, one has to use the "safe" attribute for state machines (or set them globally in the analysis settings).

I hope I'm wrong, but have Altera really changed the policy just like that? Why can't Quartus just preserve the "others" logic whenever I specify it explicitly? Isn't it simpler for the designer to specify his state machines like this, than explicitly setting attributes?

What have been your experiences with the safe encoding, manual and automatic?

Thanks in advance