safe state machines

I am pretty certain that the "when others" has been ignored by Quartus and all other synthesis machines for at least a decade. This type of synthesis makes state-machines much slower and larger, and the bottom line is that most designs will not work if bits are randomly switching anyway(where this might be useful is if your inputs to the state-machine are asynchronous, which is generally not recommended anyway). The change a few years ago, I believe, was the addition of the safe encoding attribute. Before that it was impossible to get it to do truly safe encoding(and again, most other synthesis tools did not have a way to do it until recently). So almost every FPGA design out there does not decode that states that are "impossible" to get to without a timing failure, bit-flip from high-atmosphere particles, or something else "catastrophic". So unless you have a good understanding of why your design would have this type of failure, the when others decode is usually not a concern.

(But it is still recommended to put the when others in for RTL simulation purposes. For example, if your input is momentarily one of the 9 standard_logic values besides '1' and '0', then this condition evaluates, but it's for simulation purposes only. I don't know what conditions would really cause this, but that's what I've heard.)