safe state machines

The fact that the statement refers to reset state possibly means the discussion is in the context of having reset in the FSM. Therefore the reset will ensure that no unreachable state occurs at power up and thus any "when others" can be removed. If and due to an operational timing glitch an unreachable state occured then it is the fault of timing, the remedy is to not have timing problem in the first place. I know many designs(fpga or asic) that depend entirely on the startup value of a signal and don't care about operational glitches - not very healthy but in practice it works in a good design.