safe state machines

My unerstanding was that, the "others" case might be redundant in the VHDL simulation as you've covered every value of the enumerated state type; but this enumerated type is converted to a binary encoding during synthesis. This encoding might therefore not cover all states unless you have included the "others".

The Quartus handbook that I have isn't entirely clear but seems to back up what you're saying, eliben:

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"...synthesis tools detect if state machine logic is unreachable and minimize or remove the logic."

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I think that this is saying that the synthesis tools might / will remove any logic associated with the "others" if it thinks it can optimise it. If you're using third party synthesis tools then I'd check what they say. The manual doesn't explicitly say what Quartus does either - it seems a comment on synthesis tools generally - but I guess the implication is that Quartus will ignore the "others".

Also:

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"If the state machine is implemented as safe, the recovery logic forces its transition from an illegal state to the reset state."

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I guess it's something that Altera could do with clarifying - why ignore the "others" part of the case statement? It just seems a bit daft to me to explicitly ignore a piece of code.