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Thank you FvM for the helpful explanations. In troubleshooting my FPGA resetting issue I made all IOs quiet (almost all of them) and I still had the FPGA reset due to core supply voltage noise so not I/O supplies noise. I was able to eliminate the resetting issue by changing the decoupling capacitors on the core supply VCCINT. Now it does not reset but I put an oscilloscope on the VCCINT on one of the decoupling capacitors on the bottom side of the PCB under the FPGA and it shows noise as high as about 180mV_pk_pk. My concern is that this noise is seen by the core logic blocks inside the FPGA so I am not sure if the timing models used in Quartus II account for such a high noise. Does anyone know if this magnitude of noise is expected? Have anyone measured the noise on VCCINT and got similar values?
Thank you,
Cosmin
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180mV (if accurate) is on the high side for noise on the power rail. However, unless you are very careful this can easily be a false measurement ... if you use a high impedance scope probe with a flying ground lead, you will get induced noise that is not really in the circuit. I have found the only way to reliably measure the noise on a power rail is to use a length of 50ohm coax soldered directly across a decoupling cap (or remove the cap and solder the coax to the pads with no extra lead length). Then run the coax into the 50ohm input of a high performance scope, and you will see what is really happening.
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