S-parameter model of the power delivery network in Quartus functional simulation

Thank you FvM for the helpful explanations. In troubleshooting my FPGA resetting issue I made all IOs quiet (almost all of them) and I still had the FPGA reset due to core supply voltage noise so not I/O supplies noise. I was able to eliminate the resetting issue by changing the decoupling capacitors on the core supply VCCINT. Now it does not reset but I put an oscilloscope on the VCCINT on one of the decoupling capacitors on the bottom side of the PCB under the FPGA and it shows noise as high as about 180mV_pk_pk. My concern is that this noise is seen by the core logic blocks inside the FPGA so I am not sure if the timing models used in Quartus II account for such a high noise. Does anyone know if this magnitude of noise is expected? Have anyone measured the noise on VCCINT and got similar values?