S-parameter model of the power delivery network in Quartus functional simulation

I don't believe that "self generated supply noise" is a suitable term to analyze signal integrity problems in FPGA interconnect. The effect is usually described as "ground bounce" generated by switching outputs. It can be modeled in a first order by ground pin inductance.

As already explained, FPGA timing analysis doesn't model signal integrity problems specifically, but you can account for it by an increased jitter margin. Tools like Hyperlynx are used for an in-depth analysis of PCB interconnect.

From a practician's viewpoint, instead of analyzing ground bounce details, you'll usually try to avoid its effect by using differential signaling for critical signals.