S-parameter model of the power delivery network in Quartus functional simulation

You don't say what device family in particular you are looking at (CycloneIV, V, Max, Stratix, ...) but have you read the detailed electrical data sheets for the family/device you are looking at? They have pretty detailed specs on PLL characteristics (jitter, etc).

The 'set_clock_uncertainty' timequest command allows adding additional jitter/uncertainty to a clock rail if necessary. Are you aware of this? (in answer to question one). This would apply to Quartus place/route timing calculations, not modelsim simulation before place/route. How much extra jitter to add however is going to be a guess, unless you can derive the power supply noise to clock jitter transfer function (not easy without the detailed circuit level design of the FPGA).

In answer to question two, I have never seen such a tool that uses s-params for FPGA timing. Sounds like a good PhD project.

Backing up to square one, why are you so concerned about clock jitter? Is your application some how very critical in this respect?