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Not possible. ModelSim/Quartus are digital logic simulators only. What you require is analog circuit simulation capability; e.g. something like LinearTech LTspiceIV or Cadence PSpice.
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Thank you ak6dn,
I don't have experience in FPGA designs but from my other design experience I know that timing margins in logic design depend on propagation delay and clock jitter, which both are very dependent on the self-generated supply noise on the FPGA power rails. Self-generated supply noise depends on the values and locations of decoupling capacitors on the PCB, which is a user dependent decision, so timing models in Quartus II cannot know this information. I assume Quartus II models estimate some (expected) supply noise but the simulator does not know if the estimation is accurate or not because ultimately this depends on the FPGA user.
So I am trying to put an s-parameter model of the FPGA PDN (that includes the decoupling capacitors on the PCB) in a circuit simulator to estimate the clock jitter and gate delay variations on FPGA. I have two follow up questions:
1. If I am able to use a Spice simulator (LT Spice for example) and find out the clock jitter on the FPGA due to the dynamic current variation of my specific design, is it a way to insert this jitter value in Quartus II timing analysis or ModelSim functional simulation to see how it affects my timing margin?
2. Does anyone know of any simulation tool, simulation method, or simulation example that uses an s-parameter model of the power delivery network to simulate the timing on an FPGA?
Best Wishes,
Cosmin
Honored Contributor
