Forum Discussion
Altera_Forum
Honored Contributor
13 years agoIn the modelsim gui, simply type
Modelsim> vlib rtl_work Modelsim> vmap work rtl_work Modelsim> vlog FA.v Modelsim> vsim FA Modelsim> add wave * Modelsim> run 10 us Your FA.v design should be a testbench, i.e., something that provides stimulus to a component. Normally you would have FA.v and FA_tb.v, where FA_tb.v instantiates the component in FA.v Cheers, Dave