Running a batch file before compiling

You can generate Timestamp in QSYS custom IP, just add single line code# source "data_time.tcl"# in your .tcl file.

#  TCL File Generated by Component Editor 16.1#  Mon Dec 19 19:08:17 JST 2016#  DO NOT MODIFY
#  #  spi_ctrl "SPI Slave Controllor" v1.3#  Ben.C.Kevin 2016.12.19.19:08:17#  #  
#  #  request TCL package from ACDS 16.1#  
package require -exact qsys 16.1
#  #  module spi_ctrl#  
set_module_property DESCRIPTION ""
set_module_property NAME spi_ctrl
set_module_property VERSION 1.3
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP SPI
set_module_property AUTHOR Ben.C.Kevin
set_module_property DISPLAY_NAME "SPI Slave Controllor"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#  #  file sets#  
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL spi_ctrl
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file spi_ctrl.vhd VHDL PATH spi_ctrl.vhd TOP_LEVEL_FILE
add_fileset_file spi_slave.vhd VHDL PATH spi_slave.vhd
add_fileset_file true_dual_port_ram_single_clock.vhd VHDL PATH true_dual_port_ram_single_clock.vhd
add_fileset_file spi_ver_reg.vhd VHDL PATH spi_ver_reg.vhd
add_fileset_file data_time.tcl OTHER PATH data_time.tcl CONTAINS_INLINE_CONFIGURATION
#  #  parameters#  
add_parameter N POSITIVE 8 ""
set_parameter_property N DEFAULT_VALUE 8
set_parameter_property N DISPLAY_NAME N
set_parameter_property N TYPE POSITIVE
set_parameter_property N UNITS None
set_parameter_property N ALLOWED_RANGES 1:2147483647
set_parameter_property N DESCRIPTION ""
set_parameter_property N HDL_PARAMETER true
add_parameter CPOL STD_LOGIC 0
set_parameter_property CPOL DEFAULT_VALUE 0
set_parameter_property CPOL DISPLAY_NAME CPOL
set_parameter_property CPOL TYPE STD_LOGIC
set_parameter_property CPOL UNITS None
set_parameter_property CPOL ALLOWED_RANGES 0:1
set_parameter_property CPOL HDL_PARAMETER true
add_parameter CPHA STD_LOGIC 0
set_parameter_property CPHA DEFAULT_VALUE 0
set_parameter_property CPHA DISPLAY_NAME CPHA
set_parameter_property CPHA TYPE STD_LOGIC
set_parameter_property CPHA UNITS None
set_parameter_property CPHA ALLOWED_RANGES 0:1
set_parameter_property CPHA HDL_PARAMETER true
add_parameter PREFETCH POSITIVE 3
set_parameter_property PREFETCH DEFAULT_VALUE 3
set_parameter_property PREFETCH DISPLAY_NAME PREFETCH
set_parameter_property PREFETCH TYPE POSITIVE
set_parameter_property PREFETCH UNITS None
set_parameter_property PREFETCH ALLOWED_RANGES 1:8
set_parameter_property PREFETCH HDL_PARAMETER true
add_parameter BUFF_ADDR_WIDTH POSITIVE 10
set_parameter_property BUFF_ADDR_WIDTH DEFAULT_VALUE 10
set_parameter_property BUFF_ADDR_WIDTH DISPLAY_NAME PAGE_BUF_SIZE
set_parameter_property BUFF_ADDR_WIDTH TYPE POSITIVE
set_parameter_property BUFF_ADDR_WIDTH UNITS None
set_parameter_property BUFF_ADDR_WIDTH ALLOWED_RANGES 1:15
set_parameter_property BUFF_ADDR_WIDTH HDL_PARAMETER true
set_parameter_property BUFF_ADDR_WIDTH DESCRIPTION "2's power 14 is 64KByte"
#  #  display items#  
#  #  connection point reset_sink#  
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink reset_n_i reset_n Input 1
#  #  connection point clock_sink#  
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk_i clk Input 1
#  #  connection point conduit_end#  
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock_sink
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end do_transfer_o debug_o Output 1
add_interface_port conduit_end spi_miso_o miso_o Output 1
add_interface_port conduit_end spi_mosi_i mosi_i Input 1
add_interface_port conduit_end spi_sck_i sck_i Input 1
add_interface_port conduit_end spi_ssel_i ss_n_i Input 1
#  #  connection point avalon_slave#  
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock_sink
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave avl_cs chipselect Input 1
add_interface_port avalon_slave avl_addr address Input 18
add_interface_port avalon_slave avl_d_i writedata Input 32
add_interface_port avalon_slave avl_we_i write Input 1
add_interface_port avalon_slave avl_wait_o waitrequest Output 1
add_interface_port avalon_slave avl_d_o readdata Output 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
source "data_time.tcl"

#  ================================================================================# #  Build timestamp#  #  Create By  :myfingerhurt#  Create Date: 2014/12/18# #  ================================================================================
    set timestamp 
    puts " - Build timestamp  ($timestamp 0x)"
    set buildDate X""
    set buildTime X""
    puts "$buildDate $buildTime "
   #  Create a VHDL file for output
    set outputFileName "spi_ver_reg.vhd"
    set outputFile 
    
   #  Output the Verilog source
    puts $outputFile "--This file is Auto Generated BY datetime.tcl--"
    puts $outputFile "--Create DateTime: $buildDate $buildTime"
    puts $outputFile ""
    puts $outputFile "LIBRARY ieee;\nUSE ieee.std_logic_1164.ALL;"
    puts $outputFile "-------------------------------------------------------------------------------"
    puts $outputFile "-- The package is here"
    puts $outputFile "-------------------------------------------------------------------------------"
    puts $outputFile "ENTITY spi_ver_reg IS"
    puts $outputFile "    PORT ("
    puts $outputFile "        oDate : OUT STD_LOGIC_VECTOR(31 downto 0);"
    puts $outputFile "        oTime : OUT STD_LOGIC_VECTOR(23 downto 0)"
    puts $outputFile "    );"
    puts $outputFile "END spi_ver_reg;"
    puts $outputFile "-------------------------------------------------------------------------------"
    puts $outputFile "-- BODY"
    puts $outputFile "-------------------------------------------------------------------------------"
    puts $outputFile "ARCHITECTURE rtl OF spi_ver_reg IS"
    puts $outputFile "BEGIN"
    puts $outputFile "    oDate <= $buildDate;"
    puts $outputFile "    oTime <= $buildTime;"
    puts $outputFile "END rtl;"
    puts $outputFile "------------------------END OF FILE--------------------------------------------"
    close $outputFile
    
    
   #  Send confirmation message to the Messages window
    puts stdout "Generated build identification VHDL module: /$outputFileName"
    puts stdout "Date:             $buildDate"
    puts stdout "Time:             $buildTime"