Honored ContributorHi to everybody!!!
When I want to see RTL-representation of VHDL-design I use RTL Viewer. Does anybody know how to get some another representation of RTL, something like netlist but just for RTL-level? I want to make changes in the structure using RTL-representation. Thank you in advance!!!
Honored ContributorHave you tried the Quartus Grafical entry files, .bdf?
Honored ContributorThanks for your reply Tricky, but I need a possibility to change RTL representation of VHDL-design given from RTL Viewer.
Honored ContributorThat is not possible, because it would need to back annotate the source code. From the RTL viewer, you can link back to source code though, so that might be a good compromise.
Honored ContributorOk. Maybe you know, Is there any other format of RTL-represantation, something like EDIF but for RTL?
Honored ContributorYou still need to change the source. Hence why the RTL viewer is just a viewer. Why would you want to change the design post synthesis, rather than the source code?
Honored Contributorit is a part of my investigation. ok thank you for your replies.I'll think it over.
