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I have never personally done this, but Altera has a library design example here:
https://www.altera.com/support/support-resources/design-examples/design-software/opencl/library-design-example.html You can take a look at the example and see if you can fix the problem by imitating what is done by Altera.
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Hi HRZ,
I've looked at the example - actually the code I'm trying to get running is a combination of fft1d example and library2 example. I found my issue last night actually:
The XML file needs to include clock, resetn, and the 4 AvalonST signals. ADDITIONALLY (which I did not initially have), these 6 extra signals need to explicitly be included in your RTL module .vhd or .v. I think the synthesiser generates the same signals at a higher level RTL module (i.e the
fft1d.cl module) and then connects them straight to my RTL module. Because my module did not have these signals, they could not be routed anywhere, which is why the .log was complaining about these signals in the synthesised fft1d.v file.
In any case, my kernel compiled - thanks for the help.
ap29
Honored Contributor
