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I've gone over the user guide before, but it never explicitly says if a READ requires a full cycle of latency, or if it can be read immediately. Am I wrong? I'm familiar with running modelsim, was just surprised at this behavior and was wondering if there's a solution that would let me read immediately. Is there?
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What you are asking for is essentially asynchronous SRAM, i.e., the output data depends on the input address.
FPGAs contain synchronous SRAM, which is essentially asynchronous SRAM with input address, data, and control registers, and an optional output data register.
Use the IP Catalog (or MegaWizard generator on older tools) to create a single-port RAM component. Look at the little symbol it creates and you'll notice that the left-side (inputs) have registers, and depending on settings the outputs can also have registers.
This is a fundamental feature of the newer generation FPGAs, older generations like FLEX10K could have asynchronous SRAM, however, newer devices are "built for speed", and large asynchronous paths in SRAMs are slow, so those paths are cut with registers.
This "feature" is generally not a problem, since the address-to-read-data delay of 1 or 2 clocks is fine.
If that "feature" affects your design, then you could implement a RAM using logic elements. You'll want it to be small, but it will have the read timing you desire.
Cheers,
Dave
Honored Contributor
