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Altera_Forum's avatar
Altera_Forum
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9 years ago

ROM is uninferred because MIF is not supported for the family.

I'm using Quartus Prime Lite 16.1 with a MAX 10 FPGA devel kit. I used the Insert Temlplate -> VHDL -> Full Designs -> RAMs and ROM's -> Dual-Port ROM to generate a sample VHDL code that ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Found one more odditty. Synthesis (Quartus Prime Lite 16.1) is in fact generating a mif file (see attached) from my init_rom function; it just uses it to init the flip-flops instead of a block RAM. When I change the table generics, it generates the correct sine table in the file and the code functions correctly. Just not using RAM.