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Altera_Forum's avatar
Altera_Forum
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9 years ago

ROM is uninferred because MIF is not supported for the family.

I'm using Quartus Prime Lite 16.1 with a MAX 10 FPGA devel kit. I used the Insert Temlplate -> VHDL -> Full Designs -> RAMs and ROM's -> Dual-Port ROM to generate a sample VHDL code that ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Tricky,

Thanks for the suggestion. I had considered just instantiating an ALTSYNCH_RAM. Looking at the .vhd file created by the Wizards, it looks like I just need to include:

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

and then there are alot of generics that specify the nature of the RAM. There is one for INIT_FILE:

http://quartushelp.altera.com/14.1/mergedprojects/hdl/mega/mega_file_altsynch_ram.htm

However, that does not really solve my problem. My goal was to have a parameterized DDS (see attached). The actual init function uses SIN() function from MATH.REAL library. I guess the tools create a MIF file for some device families. So I will still need an external program to create the MIF file for a particular set of parameters.