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And another question, If I want to change my data to 32 bits, instead of 8 bits, how should change this part?
type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);
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type mem_type is array (0 to 7) of std_logic_vector(31 downto 0);
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Also, if I need to read these data back to do some operation on them, can I just simply get my output I read from my memory and connect it to my other entity that I'm doing that specific operation? Or do I need to call every sample, if that make any sense. Since I have 8 samples, and I need to do this on each sample, am I gonna get one sample at a time? or all of them together? I have a very unclear view on how to deal with these output I'm reading from the array.
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Forget the code. Step away from the code. Now get out some paper and draw the circuit you're trying to achieve. If you cannot do this, you should not be writing VHDL or Verilog. VHDL is NOT like writing C. if you dont understand the circuit you're creating, you cannot expect to write VHDL.
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