Forum Discussion
Niv_Amsalem
New Contributor
3 years agoRom implementation on Quartus
Hi All,
i am working on a project with Stratix 10 Device.
i have tried to implement System Verilog Rom (not as IP) in my design.
the problem is that some ROM's Quartus translate correctly as a ...
SyafieqS
Super Contributor
3 years agoMay I know if there is any update from previous reply?
As the snippet you posted is different from the Quartus template
- Niv_Amsalem3 years ago
New Contributor
Hi,
i suspect that the Synplify Premier in the Mapping stage determine if it's implemented as Registers or not.
so it's under investigation.
i will update once i will have an answer.
Thanks
Niv.