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Niv_Amsalem's avatar
Niv_Amsalem
Icon for New Contributor rankNew Contributor
3 years ago

Rom implementation on Quartus

Hi All, i am working on a project with Stratix 10 Device. i have tried to implement System Verilog Rom (not as IP) in my design. the problem is that some ROM's Quartus translate correctly as a ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Looking at a template in the text editor, there is no CS signal used. Also, why are you using a generate statement and a genvar that you are not using anywhere?