Ripple clock caused by State Machines

Ripple clock means that a register output signal, e.g. any of the state variables or triggers from the state machines is feed to a register clock input. In VHDL, this is done by an edge sensitive expression e.g. (signal'EVENT AND signal='1') resepectively rising_edge(signal).

As said by all contributors, this should be strictly avoided in a synchronous design. I think, the problematic location in your code should be easily detectable by tracing the signals mentioned in the Quartus warning.