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Altera_Forum's avatar
Altera_Forum
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16 years ago

Ripple clock caused by State Machines

Hi, I'm trying to make a project, so I have 6 state machines which are related/cascaded. I have 3 state machines layers and a clock flow over those state machines as follows: Layer 1: FSM...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Ok guys,

tnx for help me. I'll try to find out a little more.

FvM:

Maybe it didn't appear because there is an other logic part (the other FSM) that is dependent of this first one (when I say dependent means a situation quite similar to this that I showed. There is other FSM which is "activated" by a signal from the second FSM showed in code). Anyway, I appreciate your help. Unfortunately, I can't show more code than I've already showed.

alt1000:

The tips was very good, thank you too. But I've already did those things.

Look, I understand that even only one clock domain can cause a little delay comparing bigger path and littler path, can't it? So I think to myself that this could be the issue for my design. On the other hand, this other logic part isn't too bigger than those first ones. So... if those parts of my logic don't cause ripple clock action, why an other similar logic do it?

my best,

higor