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Altera_Forum
Honored Contributor
Honored ContributorRipple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks
Many threads on this forum involve clocks that are not driven directly by device pins or PLLs. This thread addresses design considerations for clocks driven by registers or combinational logic. ...
Altera_ForumHonored Contributor
Honored ContributorHi Brad. This article is very helpful for my current work. Will this article be added to the Altera Application Note? It will be a good one!
BTW, do you mind if I translate this article into Chinese on my blog for more Chinese engineers to read?
