Ripple and gated clocks: clock dividers, clock muxes, and other logic-driven clocks

If you have hold violations for data paths going to or from the derived clock domain, then have the Fitter try to fix them. At "Assignments --> Settings --> Fitter Settings (category on left side)", set "Optimize Hold Timing" to "All Paths".

This setting will cause the Fitter to insert routing delay in the data path between registers to avoid hold violations.

Even if this setting succeeds in eliminating all reported violations, the uncertainty considerations for on-die variation described for design guideline# 3 still apply.