Ridiculous interconnect timing between related clocks

Thank you for commenting back. It is also good to know that I am not alone seeing this behavior on the A10 P&R. Before you go too far with multi-cycle constraints try to place regions for your major logic in vertical direction (S5 had horizontal direction preference). You can look up a10_ref OpenCL BSP for reference. Each region ~ 80% full. And try to push away from you regions unrelated logic like so:

set_instance_assignment -name PLACE_REGION "8 119 22 137" -to top|your_logic_instance

set_instance_assignment -name RESERVE_PLACE_REGION ON -to top|your_logic_instance

set_instance_assignment -name CORE_ONLY_PLACE_REGION OFF -to top|your_logic_instance

set_instance_assignment -name ROUTE_REGION -to top|your_logic_instance "8 119 22 137"

X/Y numbers are out of my design and they should change or your placement.

The idea is to spread the logic vertically, so P&R would not make the "mess" in the center of the chip. This should gain you better chances of routing having less segments and therefore less delay.