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Altera_Forum's avatar
Altera_Forum
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8 years ago

Ridiculous interconnect timing between related clocks

I'm trying to finalize a design in an Arria 10, using Quartus Prime Pro 16.1 , where a signal is passed from a global clock to a related peripheral clock of the same frequency (they are both derived ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

This is part of a design using the 10G transceivers. The registers on the peripheral clocks interact directly with the PHY, the global clock is for everything else. It's all part of an experiment to derive the device clock from the recovered transceiver clock...

I'm not convinced that this is just representing skew though - should that not be represented as part of the clock path rather than the data path?