Honored Contributor
Honored ContributorNo, it isn't just you ...
I also get annoyed by the tons of warning messages generated by Altera's own IP. Try using a HPC II DDR2 memory controller and you get those 125 warnings about mismatches in their Verilog code. Add in a GX block and get one hundred more. Now you have to slowly skim through the warning messages to find the ones that do matter, in first degree those which are raised in your own code, then wonder whether the ones raised in Altera and Third-Party code are the result of your work, or just the result of their sloppiness? In C-programming there is a saying : "A warning is an error waiting to happen". I personally raise warnings into errors and resolve them. But that would get us nowhere in Quartus II ...
