Forum Discussion

AWilc1's avatar
AWilc1
Icon for New Contributor rankNew Contributor
7 years ago
Solved

Reversing a bus in SystemVerilog

Is there a way to reverse a bus in systemverilog? I am trying to do: genvar j; generate for ( j=0 ; j < 256 ; j=j+1 ) begin out[j] <= in[256-j]; end endgenerate But when I compile in ...
  • dave_59's avatar
    dave_59
    7 years ago

    The problem is with the procedural assignment statement inside your generate loop. Assuming out is declared as a wire, you need to change it to

    for (genvar j=0j<256;j++)
     assign out[j] = in[256-j];

    But there us a much simpler way of writing this without a loop using the streaming operator

    assign out = {<<{in}};
dave_59's avatar
dave_59
Icon for New Contributor rankNew Contributor
7 years ago

The problem is with the procedural assignment statement inside your generate loop. Assuming out is declared as a wire, you need to change it to

for (genvar j=0j<256;j++)
     assign out[j] = in[256-j];

But there us a much simpler way of writing this without a loop using the streaming operator

assign out = {<<{in}};