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Daniel99's avatar
Daniel99
Icon for New Contributor rankNew Contributor
1 year ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

I attached the same design used above. If you change the I/O standard to 1.8V, you'll see the restricted Fmax aligns more closely with the clock tree performance numbers. For the LVDS I/O standard, we don’t document its maximum clock frequency — we only specify 500 Mbps, which corresponds to a 250 MHz clock for double data rate operation.

The 500 Mbps limit is for data transmission — with DDR input registers capturing data on both edges of a 250 MHz clock. If you’re feeding a 500 MHz clock into an LVDS pin (single-ended clock), this exceeds the intended use case and specification — unless Quartus timing and board SI confirm it's safe.