New Contributor
Super ContributorProbably, some sample of verilog code will help:
module lvds_ddr_in (
input wire lvds_clk, // 250 MHz clock
input wire lvds_data, // 500 Mbps LVDS data
output reg data_rise, // Data sampled on rising edge
output reg data_fall // Data sampled on falling edge
);
always @(posedge lvds_clk)
data_rise <= lvds_data;
always @(negedge lvds_clk)
data_fall <= lvds_data;
endmodule
lvds_data must be assigned to a pin with IOSTANDARD "LVDS" in your .qsf:
set_location_assignment PIN_A1 -to lvds_data
set_instance_assignment -name IO_STANDARD "LVDS" -to lvds_data
lvds_clk should be the recovered clock or forwarded clock — also through an LVDS pair if needed.
To combine data_rise and data_fall into a parallel word (deserialization), shift them into a register array at the system clock domain.
1:4 Deserializer Example
module lvds_ddr_4bit_in (
input wire lvds_clk, // 250 MHz clock
input wire lvds_data,
output reg [3:0] parallel_data
);
reg [3:0] shift_reg;
always @(posedge lvds_clk) begin
shift_reg[3:2] <= {shift_reg[1:0]};
shift_reg[1] <= lvds_data;
end
always @(negedge lvds_clk) begin
shift_reg[0] <= lvds_data;
parallel_data <= shift_reg;
end
endmodule
