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Daniel99's avatar
Daniel99
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8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
Daniel99's avatar
Daniel99
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8 months ago

Sorry, my mistake, I meant to say:

"Since there is no way I can tell Quartus about which differential voltage swing I will apply to an LVDS input pin (or is there?), it will, in my case, give me the restricted Fmax based on table 29 and not from table 19."

But if table 19 assumes double-data-rate for LVDS and LVPECL it is a pity that this is not mentioned.

Frank, you say "Timing analysis tells you if restricted Fmax is caused by I/O "(max IO toggle rate)" or core logic speed "(tmin)" but for my design it is reported as "Restricted Fmax due to minimum period (tmin)" and not I/O toggle rate, and from Kennys comments it is clear that the restricted Fmax I get is in fact due to LVDS frequency limitations as stated in table 29, and not from table 20 about Clock tree performance, even though reported as (tmin).

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    8 months ago

    Hi,
    restricted Fmax (tmin) refers to core clock limitation as far as I see. You can check by testwise selecting C6 speed grade, timing analysis reports I/O related Fmax then.

    There is no voltage swing dependance specified in table 19, just common voltage depedendance.

    Table 19 doesn't specifically assume double data rate, you however need double data rate input registers to process data rates up to 700 Mbps.