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Daniel99's avatar
Daniel99
Icon for New Contributor rankNew Contributor
8 months ago

Restricted Fmax due to minimum period

I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin....
Timing
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
8 months ago

Hi,
there seems to be a misunderstanding in your comparison of Cyclone 10 LP datasheet table 19 (max. LVDS data rate) and table 20 (clock tree performance). Table 19 specifies data rate in Mbps, table 20 clock frequency in MHz. Date rate of a LVDS signal is however double the signal frequency. E.g. a LVDS (double data rate) signal with 500 Mbps maximal toggle rate appears as 250 MHz square wave.

Clock tree performance and specifically minimal clock pulse width has nothing to do with IO speed, it's ruled by LE register switching behaviour. You might be able to clock your design above restricted Fmax, but it's not guaranteed to work.

Regards

Frank

Additional comment. Timing analysis tells you if restricted Fmax is caused by I/O "(max IO toggle rate)" or core logic speed "(tmin)".