Restricted Fmax due to minimum period

Thanks for your design,

Upon analysis, this touches on the distinction between achievable Fmax and device-limited Fmax (or restricted Fmax) in Quartus for Cyclone 10 LP devices. Let's break down what you're seeing.

Key Definitions

Fmax (unrestricted):

This is the frequency at which the logic in your design could theoretically run, based on post-fitting delays and your specific logic path. It reflects the performance limited by your design and fitting.

Restricted Fmax (due to minimum period restriction):

This is the frequency constrained by silicon-level device limitations like datasheet specs. In your case, it's Table 20 of the Cyclone 10 LP datasheet which gives a maximum input clock frequency for I/O standards and IOE usage.

Your Observations Explained

Let's break down your cases with interpretation:

Speed Grade Fmax (unrestricted) Restricted Fmax Table 20 Limit Comment

C8 866.5 MHz 402.09 MHz 402 MHz Quartus meets the datasheet restriction.

A7 939.85 MHz 402.09 MHz 402 MHz Device is faster, but still capped by I/O limit.

I7 961.54 MHz 403.06 MHz ~403 MHz Slightly better I/O spec due to industrial grade.

C6 1112.35 MHz 438.02 MHz 438 MHz Faster speed grade allows higher I/O toggle rate.

The Fmax (unrestricted) is higher with better speed grades because the design's flip-flops and interconnects are faster. However, the Restricted Fmax doesn't budge unless the IOE or clock input block limits change per the device datasheet.

Why the Restricted Fmax Doesn’t Increase (Much)

The restricted Fmax is not a limitation of your logic, but of the I/O standard and IOE circuitry used with that clock pin (e.g., LVDS input buffer and IOE PLL pre-processing). This is a hard datasheet constraint — no matter how fast your logic is, Quartus limits this path based on guaranteed device performance across voltage/temp corners.

That’s why even when your unrestricted Fmax goes up (due to better speed grades), the restricted Fmax follows only what the datasheet allows.

Example:

For C8 and A7, the max toggle rate for LVDS inputs is 402 MHz

For C6, it goes up to 438 MHz

This is what Quartus uses as a hard cap when calculating “Restricted Fmax”.

I attached another design for you to play with, usually, when both setup and hold fail at the same I/O path, it's often due to the physical I/O timing limitations — not your logic design.