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Altera_Forum's avatar
Altera_Forum
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12 years ago

Reset Polarity in QSYS

Hi,

how can I manage different reset polarities in QSys?

I have some blocks (PIO) that need reset_n and some blocks (DMA, RAM, custom) that need reset.

Is there a block that negates reset logic?

I'm asking that becauyse I've started a project from the PCI_Express_in_Qsys_Example_Designs found in the Altera Wiki.

It uses DMA and other logics which have a positive reset polarity but I have added some blocks that use negative edge (PIO).

I've also added the Jtag-to-Avalon Master for debug purposes and when I try to access the Avalon bus it tells me that the channel is busy after waiting for 60 seconds.

I've tried jtag_debug_sample_reset and returns "1".

Now with reset at "1" a lot of peripherals are in reset state and I think that's the cause about the problem.

How can I manage it?

Thanks

Luca

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    QSys uses the signal role to know if it must be inverted. If the signal role ends with _n, it will automatically invert it. When using the component editor, QSys will automatically use the _n role if the signal name ends with _n.

    So as long as your component blocks are well defined, QSys should cope with any reset polarity. In my experience the generated QSys instance always uses a active low reset signal on the top level though.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Also when you define your component make sure to define the reset synchronization necessary for your component. By default the tools will assume your component requires a reset that is asynchronously reset, and synchronously taken out of reset. If you need a different reset behavior for your component you can let the tools know by setting the "Synchronous edge" selection box appropriately in the "Interfaces" tab of the component editor (or set it in the .tcl file for your component directly if you know the API).