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Altera_Forum's avatar
Altera_Forum
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10 years ago

Request for help in VHDL troubleshooting

Hi all, I am a new to programming of VHDL to FPGA. Recently tried experimenting with a code from a book and during simulation, it was functioning perfectly. However after i programmed into...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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it seems You should check sensor4 ) 

sensor24 <= sensor2 & sensor4

and 

WHEN Ain =>
CASE Sensor24 IS
WHEN "11" => state <= Ain;
WHEN "10" => state <= ABout;
WHEN "01" => state <= Bstop;
WHEN "00" => state <= ABout;
WHEN OTHERS => state <= ABout;
END CASE;

--- Quote End ---

Hi Alex96,

Thanks for the pointers.

Mind sharing the concerns with sensor4?