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Altera_Forum's avatar
Altera_Forum
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10 years ago

Request for help in VHDL troubleshooting

Hi all, I am a new to programming of VHDL to FPGA. Recently tried experimenting with a code from a book and during simulation, it was functioning perfectly. However after i programmed into...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Your diagram shows that the reset signal is constant '1' - why?

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Hi tricky, good observation..

I have set it to active '0' instead..