Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Request for help in VHDL troubleshooting

Hi all, I am a new to programming of VHDL to FPGA. Recently tried experimenting with a code from a book and during simulation, it was functioning perfectly. However after i programmed into...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

There are plenty of tutorial websites. A testbench is some VHDL code that stimulates your design under test. It doesnt have to be synthesisable and you can do plenty of "programming" like things. For example, to generate a clock, you can write: 


signal clk : std_logic := '0';
....
clk <= not clk after 5 ns; -- 100 Mhz clock