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Altera_Forum
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12 years ago

replacing button press signal with control from another VHDL component

I have a VHDL component, where normally the reset signal is given by pressing a button.

Now I want to use another VHDL component to send the reset signal. The problem is that in a normal button press, the reset signal goes from low to high then back to low. If i were to use a second VHDL component to send the reset signal I would have to set it as high then write to the port again to set it back to low. How long should I wait before i reset the signal to low?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    How long should I wait before i reset the signal to low?

    --- Quote End ---

    In either case, the reset signal should route through a reset synchronizer component, such that the reset output asserts with respect to the relative clock for that reset domain, and asynchronously deasserts. I believe the Quartus handbook has a discussion on this.

    The reset signal would only need to be active for a short time, i.e., on the order of a few clock periods (which I assume you have as something like 50MHz). Its unlikely that you can toggle an I/O pin that quickly from software, assuming of course that two writes are not pipelined and written on consecutive bus cycles, but in that case you could just write the software to toggle the I/O low, read the register (which ensures the write is complete), and then toggle it high.

    Cheers,

    Dave