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How long should I wait before i reset the signal to low?
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In either case, the reset signal should route through a reset synchronizer component, such that the reset output asserts with respect to the relative clock for that reset domain, and asynchronously deasserts. I believe the Quartus handbook has a discussion on this.
The reset signal would only need to be active for a short time, i.e., on the order of a few clock periods (which I assume you have as something like 50MHz). Its unlikely that you can toggle an I/O pin that quickly from software, assuming of course that two writes are not pipelined and written on consecutive bus cycles, but in that case you could just write the software to toggle the I/O low, read the register (which ensures the write is complete), and then toggle it high.
Cheers,
Dave
Honored Contributor
