i have process I need to now implement as ROM. process (count, outi, run) --converter begin if (run = '1') then -- run is a physical switch case count is -- count is the current value of a 2 bit counter when "00" => outi <= "1000"; when "01" => outi <= "0100"; when "10" => outi <= "0001"; when "11" => outi <= "0010"; when others => outi <= "0000"; end case; end if; end process; The output outi is assigned to LEDS outside the process. I have created 1 port ram and created a mif file that looks like this Addr +0 +1 +2 +3 ASCII 0 1000 0100 0001 0010 ... But I'm not sure what exactly I need to do now. I'm very to new to VHDL and FPGAs in general.

The question is, what is wrong with the current decoder? What code have you written already, and what are the end goals? For a ROM you have a few options: 1. Use a wizard generated ROM, initialise with a .mif file 2. Define a constant and then follow the ROM template (available in the HDL coding guidelines of the Quartus Manual - and/or you can generate the template in Quartus) 3. Keep with the decoder structure, but add a clock. What do you need us to help with?

If indeed you want to use the 1-port RAM as a ROM, you'd need to remove your decoder logic (the case statement) and instantiate the RAM in your design, attaching count to the address input of the RAM and outi to the output of the RAM.

--- Quote Start --- If indeed you want to use the 1-port RAM as a ROM, you'd need to remove your decoder logic (the case statement) and instantiate the RAM in your design, attaching count to the address input of the RAM and outi to the output of the RAM. --- Quote End --- You can infer a ROM from decoder logic, if it is clocked. See "inferring ROM" from the Quartus HDL coding guidelines

--- Quote Start --- If indeed you want to use the 1-port RAM as a ROM, you'd need to remove your decoder logic (the case statement) and instantiate the RAM in your design, attaching count to the address input of the RAM and outi to the output of the RAM. --- Quote End --- sorry for really late reply. i forgot oops. I have actually done that with block diagrams but I want to do it using only vhdl now I just don't know how I'd go about doing that

--- Quote Start --- sorry for really late reply. i forgot oops. I have actually done that with block diagrams but I want to do it using only vhdl now I just don't know how I'd go about doing that --- Quote End --- Have you read the quartus handbook, the section on HDL coding guidelines? https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf Specifically, Page 12-27 - Inferring ROM Functions from HDL Code

Altera_Forum

Honored Contributor

8 years ago

Replacing a process with 1-port RAM

i have process I need to now implement as ROM.

process (count, outi, run) --converter
     begin
        if (run = '1') then -- run is a physical switch
        case count is       -- count is the current value of a 2 bit counter
            when "00" =>
                outi <= "1000"; 
            when "01" =>
                outi <= "0100";
            when "10" =>
                outi <= "0001";
            when "11" =>
                outi <= "0010";    
            when others =>
                outi <= "0000";
            end case;
        end if;
     end process;

The output outi is assigned to LEDS outside the process.

I have created 1 port ram and created a mif file that looks like this

Addr

ASCII

1000

0100

0001

0010

...

But I'm not sure what exactly I need to do now.

I'm very to new to VHDL and FPGAs in general.

Forum Discussion

Replacing a process with 1-port RAM

21 Replies

Recent Discussions

When you double click on a word, the other instances do not highlight due to the Find Box being open

jtagserver.exe causing BSOD together with ftdi driver

Automatically added negative node for TDS output doesn't work with Agilex 5

Agilex3 - unknown IDCODE

Signal Tap - *** Fatal Error: Segment Violation