Replacing a process with 1-port RAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity school is
    Port ( CLOCK_50 : in std_logic;
              run : in std_logic;
              dir : in std_logic;
              step : out std_logic_vector (1 downto 0);
              led : out std_logic_vector(3 downto 0);
              slow_fast : in std_logic
     );
end school;
architecture Behavioral of school is
signal divider : std_logic_vector (22 downto 0);
signal count : std_logic_vector (1 downto 0);
signal current_clk : std_logic; 
component ROM IS
    PORT
    (
        address        : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
        clock        : IN STD_LOGIC  := '1';
        data        : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
        wren        : IN STD_LOGIC ;
        q        : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
    );
END component;
begin
      U1 : ROM PORT MAP 
(
    clock => current_clk, 
    address => count,
    q => led,
    wren => '0',
    data => "0000"
);
     process (divider, CLOCK_50)
     begin
     if rising_edge(CLOCK_50) then
        divider <= divider + 1; 
     end if;
     end process;
     
     process (run, divider, current_clk, dir, count, slow_fast ) 
     begin
         if slow_fast = '1' then 
            current_clk <= divider(0); 
         else
            current_clk <= divider(1);
         end if;
         
         if (rising_edge(current_clk) and run = '1') then  -- 
                case dir is
                    when '0' =>
                        count <= count + 1; 
                    when '1' =>
                        count <= count - 1; 
                    when others =>
                        count <= count + 1;
                end case;
        end if;
     end process;
step <= count;
end Behavioral;