Removing Loop-Carried Dependency by Inferring Shift Registers

Hi there,

I'm trying to understand an optimization described in the Best Practices guide, "Removing Loop-Carried Dependency by Inferring Shift Registers" (page 1-48). Specifically, I don't see how the optimized version of the example code used in the optimization case study is going to be translated to a pipeline with the initiation interval being 1. According to the compiler message, the loop starting at line 17 is successfully pipelined. Also, I guess the shift register size (i.e., the value of II_CYCLES) is determined by the latency of the operation at line 22, but I'm not completely sure.

So, could somebody explain how the compiler works for the code and what the generated pipeline would look like?