Register using component and port maps

Hi, I am building a 32 bit register using a 8-bit register as a component. However, I am stuck at port mapping the 8-bit register correctly, any tips/help would be appreciated.

my code so far:

----BITSTORAGE----

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.numeric_std.all;

Use ieee.std_logic_unsigned.all;

entity bitstorage is

port(bitin: in std_logic;

enout: in std_logic;

writein: in std_logic;

bitout: out std_logic);

end entity bitstorage;

architecture memlike of bitstorage is

signal q: std_logic := '0';

begin

process(writein) is

begin

if (rising_edge(writein)) then

q <= bitin;

end if;

end process;

bitout <= q when enout = '0' else 'Z';

end architecture memlike;

--------------------------------------------------------------------------------

----8-BIT REGISTER----

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.numeric_std.all;

Use ieee.std_logic_unsigned.all;

entity register8 is

port(datain: in std_logic_vector(7 downto 0);

enout: in std_logic;

writein: in std_logic;

dataout: out std_logic_vector(7 downto 0));

end entity register8;

architecture memmy of register8 is

component bitstorage

port(bitin: in std_logic;

enout: in std_logic;

writein: in std_logic;

bitout: out std_logic);

end component;

begin

c0: bitstorage port map(datain(0),enout,writein,dataout(0));

c1: bitstorage port map(datain(1),enout,writein,dataout(1));

c2: bitstorage port map(datain(2),enout,writein,dataout(2));

c3: bitstorage port map(datain(3),enout,writein,dataout(3));

c4: bitstorage port map(datain(4),enout,writein,dataout(4));

c5: bitstorage port map(datain(5),enout,writein,dataout(5));

c6: bitstorage port map(datain(6),enout,writein,dataout(6));

c7: bitstorage port map(datain(7),enout,writein,dataout(7));

end architecture memmy;

--------------------------------------------------------------------------------

---32-BIT REGISTER---

Library ieee;

Use ieee.std_logic_1164.all;

Use ieee.numeric_std.all;

Use ieee.std_logic_unsigned.all;

entity register32 is

port(datain: in std_logic_vector(31 downto 0);

enout32,enout16,enout8: in std_logic;

writein32, writein16, writein8: in std_logic;

dataout: out std_logic_vector(31 downto 0));

end entity register32;

architecture biggermem of register32 is

component register8

port(datain: in std_logic_vector(7 downto 0);

enout: in std_logic;

writein: in std_logic;

dataout: out std_logic_vector(7 downto 0));

end component;

begin

Implementing port map here

end architecture biggermem;

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